μ PD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Boundary Scan Register Status of Output Pins CQ, CQ#, QVLD and Q
Instructions
SRAM Status
Boundary Scan Register Status
CQ, CQ#, QVLD
Q
Note
EXTEST
READ (Low-Z)
NOP (High-Z)
Pad
Pad
Pad
Pad
IDCODE
SAMPLE-Z
SAMPLE
BYPASS
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
Pad
Pad
Internal
Internal
Pad
Pad
Internal
Pad
No definition
No definition
Remark
The Boundary Scan Register statuses during execution each
instruction vary according to the instruction code and SRAM
operation mode.
Boundary Scan
Register
CAPTURE
Register
There are two statuses:
Internal
Pad
: Contents of the output pin (QDR Pad) are captured
Update
SRAM
in the “CAPTURE Register” in the Boundary Scan
Pad
Register
Output
Register.
Internal : Contents of the SRAM internal output “SRAM
Output” are captured in the “CAPTURE Register”
in the Boundary Scan Register.
QDR
Pad
SRAM
Output
Driver
High-Z
JTAG ctrl
30
Data Sheet M19962EJ2V0DS
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